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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. april 1996 copyright ? intel corporation, 1996 order number: 272405-004 87c196ca/87C196CB 20 mhz advanced 16-bit chmos microcontroller with integrated can 2.0 automotive y high performance chmos 16-bit cpu (up to 20 mhz operation) y register-register architecture y up to 56 kbytes of on-chip eprom y up to 1.5 kbyte of on-chip register ram y up to 512 bytes of additional ram (code ram) y up to 16 mbyte linear address space y supports can (controller area network) specification 2.0 y 15 message objects of 8 bytes data length y 10-bit a/d with sample/hold y 38 prioritized interrupts y up to seven 8-bit (60) i/o ports y full duplex serial port (sio) with dedicated baudrate generator y full duplex synchronous serial i/o port (ssio) y interprocessor communication slave port y selectable bus timing modes for flexible interfacing y oscillator fail detection circuitry y high speed peripheral transaction server (pts) y two dedicated 16-bit high-speed compare registers y high speed capture/compare (epa) y two flexible 16-bit timer counters y flexible 8-/16-bit external bus (programmable) y programmable bus (hld/hlda) y 1.4 m s 16 x 16 multiply y 2.4 m s 32/16 divide b 40 cto a 125 c ambient device pins/package eprom reg ram code ram i/o epa sio ssio can a/d address space 87C196CB 84-pin plcc 56k 1.5k 512b 56 10 y y y 8 1 mbyte 87C196CB 100-pin qfp 56k 1.5k 512b 60 10 y y y 8 16 mbyte 87c196ca 68-pin plcc 32k 1.0k 256b 38 6 y y y 6 64 kbyte the 87c196ca/cb are new members of the mcs 96 microcontroller family. these devices are based upon the mcs 96 kx/jx microcontroller product families with enhancements ideal for automotive and industrial applications. the ca/cb are the first devices in the kx family to support networking through the integration of the can 2.0 (controller area network) peripheral on-chip. the 87C196CB offers the highests memory density of the mcs 96 microcontroller family, with 56k of on-chip eprom, 1.5k of on-chip register ram, and 512 bytes of additional ram (code ram). in addition, the 87C196CB provides up to 16 mbyte of linear address space. the 87c196ca is a sub-set of the cb, offering 32k of on-chip eprom, up to 1.0k of on-chip register ram, and 256 bytes of additional ram (code ram).
87c196ca/87C196CB the mcs 96 microcontroller family members are all high-performance microcontrollers with a 16-bit cpu. the 87C196CB is composed of the high-speed (20 mhz) macrocore with up to 16 mbyte linear address space, 56 kbytes of program eprom, up to 1.5 kbytes of register ram, and up to 512 bytes of code ram (16-bit addressing modes) with the ability to execute from this ram space. it supports the high-speed, serial commu- nications protocol can 2.0, with 15 message objects of 8 bytes data length, an 8-channel, 10-bi t/3lsb analog to digital converter with programmable s/h times, and conversion times k 20 m s at 20 mhz. it has an asynchronous/synchronous serial i/o port (sio) with a dedicated 16-bit baud rate generator, an additional synchronous serial i/o port (ssio) with full duplex master/slave transceivers, a flexible timer/counter struc- ture with prescaler, cascading, and quadrature capabilities. there are ten modularized, multiplexed, high- speed i/o for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs, and a sophisticated prioritized interrupt structure with programmable peripheral transaction server (pts) implementing several channel modes, including single/burst block transfers from any memory location to any memory location, a pwm and pwm toggle mode to be used in conjunction with the epa , and an a/d scan mode. notice: this is an advance information data sheet. the a.c. and d.c. parameters contained within this data sheet may change after full automotive temperature characterization of the device has been per- formed. contact your local sales office before finalizing the timing and d.c. characteristics of a design to verify you have the latest information. 272405 30 figure 1. 8xc196cb block diagram 2
87c196ca/87C196CB process information these devices are manufactured on p629.5, a chmos iii-e process. additional process and reli- ability information is available in intel's components quality and reliability handbook , order number 210997. all thermal impedance data is approximate for static air conditions at 1.0w of power dissipation. values will change depending on operation conditions and application. see the intel packaging handbook (or- der number 240800) for a description of intel's ther- mal impedance test methodology. 272405 2 figure 2. the 87c196ca/cb familiy nomenclature thermal characteristics device and package i ja i jc an87C196CB 35.0 c/w 11.0 c/w (84-lead plcc package) an87c196ca 36.5 c/w 10.0 c/w (68-lead plcc package) notes: 1. i ja e thermal resistance between junction and the surrounding environment (ambient) measurements are taken 1 ft. away from case in air flow environment. i jc e thermal resistance between junction and package face (case). 2. all values of i ja and i jc may fluctuate depending on the environment (with or without airflow, and how much airflow) and device power dissipation at temperature of operation. typical variations are g 2 c/w. 3. values listed are at a maximum power dissipation of 1.0w. 3
87c196ca/87C196CB 272405 14 figure 3. 84-pin plcc an87C196CB diagram 4
87c196ca/87C196CB 272405 33 figure 4. 100-pin qfp as87C196CB diagram 5
87c196ca/87C196CB 272405 3 figure 5. 68-pin plcc 87c196ca diagram 6
87c196ca/87C196CB symbol name and function v cc main supply voltage ( a 5v). v ss ,v ss1 digital circuit ground (0v). there are 7 v ss pins cb (4 on ca), all of which must be connected to a single ground plane. v ref reference for the a/d converter ( a 5v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . v pp programming voltage for eprom parts. it should be a 12.5v for programming. it is also the timing pin for the return from powerdown circuit. connect this pin with a 1 m f capacitor to v ss and a 1mohm resistor to v cc . if this function is not used, v pp may be tied to v cc . xtal1 input of the oscillator inverter and the internal clock generator. xtal2 output of the oscillator inverter. reset y reset input to the chip. input low for at least 16 state times will reset the chip. the subsequent low to high transition resynchronizes clkout and commences a 10-state time sequence in which the psw is cleared, bytes are read from 2018h, 201ah and 201ch (if enabled) loading the ccb's, and a jump to location 2080h is executed. input high for normal operation. reset y has an internal pullup. nmi a positive transition causes a non-maskable interrupt vector through memory location 203eh. if not used, this pin should be tied to v ss . may be used by intel evaluation boards. ea y input for memory select (external access). ea y equal to a high causes memory accesses to locations 0ff2000h through 0ffffffh to be directed to on-chip eprom/rom. ea y equal to a low causes accesses to these locations to be directed to off-chip memory. ea y ea 12.5v causes execution to begin in the programming mode. ea y is latched at reset. pllen selects between pll mode or pll bypass mode. this pin must be either tied high or low. pllen pin e 0, bypass pll mode. pllen pin e 1, places a 4x pll at the input (196cb only) of the crystal oscillator. allows for a low frequency crystal to drive the device (i.e., 5 mhz e 20 mhz operation). p6.4 6.7/ssio dual function i/o ports have a system function as synchronous serial i/o. two pins are clocks and two pins are data providing for full duplex capability. also lsio when not used as ssio. p6.3/t1dir dual function i/o pin. primary function is that of a bidirectional i/o pin, however, it may also be used as a timer1 direction input. the timer1 will increment when this (cb only) pin is high and decrements when this pin is low. p6.2/t1clk dual function i/o pin. primary function is that of a bidirectional i/o pin, however may also be used as a timer1 clock input. the timer1 will increment or decrement on (cb only) both positive and negative edges of this pin. p6.0 6.1/epa8 9 dual function i/o port pins. primary function is that of bidirectional i/o. system function is that of high speed capture and compare. 7
87c196ca/87C196CB symbol name and function p5.7/buswidth input for bus width selection. if ccr bit 1 is a one and ccr1 bit 2 is a one, this pin dynamically controls the buswidth of the bus cycle in progress. if buswidth is low, (cb only) an 8-bit cycle occurs, if buswidth is high, a 16-bit cycle occurs. if ccr bit 1 is ``0'' and ccr1 bit 2 is ``1'', all bus cycles are 8-bit, if ccr bit 1 is ``1'' and ccr1 bit 2 is ``0'', all bus cycles are 16-bit. ccr bit 1 e ``0'' and ccr1 bit 2 e ``0'' is illegal. also an lsio pin when not used as buswidth. p5.6/ready ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. if the pin is high, cpu operation continues in a normal manner. if the pin is low prior to the falling edge of clkout, the memory controller goes into a wait state mode until the next opositive transition in clkout occurs with ready high. when external memory is not used, ready has no effect. the max number of wait states inserted into the bus cycle is controlled by the ccr/ccr1. also an lsio if ready is not selected. p5.5/bhe y /wrh y byte high enable or write high output, as selected by the ccr. bhe y e 0 selects the bank of memory that is connected to the high byte of the data bus. a0 e 0 selects the bank of memory that is connected to the low byte. thus accesses to a 16-bit wide memory can be to the low byte only (a0 e 0, bhe y e 1), to the high byte only (a0 e 1, bhe y e 0) or both bytes (a0 e 0, bhe y e 0). if the wrh y function is selected, the pin will go low if the bus cycle is writing to an odd memory location. bhe y /wrh y is only valid during 16-bit external. also an lsio pin when not bhe/wrh y . p5.4/slpint dual function i/o pin. as a bidirectional port pin or as a system function. the system function is a slave port interrupt output pin (on ca, bidirectional port pin only). p5.3/rd y read signal output to external memory. rd y is active only during external memory reads or lsio when not used as rd y . p5.2/wr y /wrl y write and write low output to external memory, as selected by the ccr, wr y will go low for every external write, while wrl y will go low only for external writes where an even byte is being written. wr y /wrl y is active during external memory writes. also an lsio pin when not used as wr y /wrl y . p5.1/inst output high during an external memory read indicates the read is an instruction fetch. inst is valid throughout the bus cycle. inst is active only during external (cb only) memory fetches, during internal eprom fetches inst is held low. also lsio when not inst. p5.0/ale/adv y address latch enable or address valid output, as selected by ccr. both pin options provide a latch to demultiplex the address from the address/data bus. when the pin is adv y , it goes inactive (high) at the end of the bus cycle. adv y can be used as a chip select for external memory. ale/adv y is active only during external memory accesses. also lsio when not used as ale. 8
87c196ca/87C196CB symbol name and function port 3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus which has strong internal pullups. p2.7/clkout output of the internal clock generator. the frequency is the oscillator frequency. clkout has a 50% duty cycle. also lsio pin when not used as clkout. p2.6/hlda y bus hold acknowledge. active-low output indicates that the bus controller has relinquished control of the bus. occurs in response to an external device asserting the hld y signal. also lsio when not used as hlda y . p2.5/hld y bus hold. active-low signal indictes that an external device is requesting control of the bus. also lsio when not used as hld y . (cb only) p2.4/intout y interrupt output. this active-low output indicates that a pending interrupt requires use of the external bus. also lsio when not used as intout y p2.3/breq y bus request. this active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. also lsio when not used as (cb only) breq y p2.2/extint a positive transition on this pin causes a maskable interrupt vector through memory location 203ch. also lsio when not used as extint. p2.1/rxd receive data input pin for the serial i/o port. also lsio if not used as rxd. p2.0/txd transmit data output pin for the serial i/o port. also lsio if not used as txd. port 1/epa0 7 dual function i/o port pins. primary function is that of bidirectional i/o. system function is that of high speed capture and compare. epa0 and epa2 have another function of t2clk and t2dir of the timer2 timer/counter. port 0/ach0 7 8-bit high impedance input-only port. these pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. these pins are also used as inputs to eprom parts to select the programming mode. eport 8-bit bidirectional standard and i/o port. these bits are shared with the extended address bus, a16 a19 for cb plcc, a16 a23 for cb qfp. pin function is selected on (cb only) a per pin basis. txcan push-pull output to the can bus line. rxcan high impedance input-only from the can bus line. 9
87c196ca/87C196CB 87C196CB memory map address description ffffffh program memory - internal eprom or external memory ff2080h (determined by ea y pin) ff207fh special purpose memory (internal eprom or external memory) ff2000h (determined by ea y pin) ff1fffh external memory ff0600h ff05ffh internal ram (identically mapped into 00400h 005ffh) ff0400h ff03ffh external memory ff0100h ff00ffh reserved for ice ff0000h feffffh overlayed memory (external)eaccesses into memory ranges 0f0000h to feffffh will overlay page 15 (0fh) for cb qfp packageeexternal memory. (5) 0f0000h 0effffh 900 kbytes external memory 010000h 00ffffh external memory or remapped otprom (program memory) (1) 002080h 00207fh external memory or remapped otprom (special purpose memory) (1, 3) 002000h 001fffh memory mapped special function registers (sfr's) 001fe0h 001fdfh internal peripheral special function registers (sfr's) (5) 001f00h 001effh internal can peripheral memory (5) 001e00h 001dffh internal register ram 001c00h 001bffh external memory 000600h 0005ffh internal ram (code ram) 000400h (address with indirect or indexed modes) 0003ffh register ram upper register file (address with indirect or indexed modes or through windows.) (2) 000100h 10
87c196ca/87C196CB 87C196CB memory map (continued) address description 0000ffh register ram lower register file. (address with direct, indirect, or indexed modes.) (2) 000018h 000017h cpu sfr's (4) 000000h notes: 1. these areas are mapped internal eprom if the remap bit (ccb2.2) is set and ea y e 5v. otherwise they are external memory. 2. code executed in locations 0000h to 003ffh will be forced external. 3. reserved memory locations must contain 0ffh unless noted. 4. reserved sfr bit locations must be written with 0. 5. refer to 8xc196cb user's guide for sfr, can and paging descriptions. 87c196ca memory map address description 00ffffh external memory 00a000h 009fffh internal eprom (32 kbytes) 002080h 00207fh (determined by ea y pin) reserved memory (internal eprom or external memory) 002000h 001fffh memory mapped special function registers (sfr's) 001fe0h 001fdfh internal special function registers (sfr's) (1) 001f00h 001effh internal can peripheral memory 001e00h 001dffh external memory 000500h 0004ffh (address with indirect or indexed modes) internal ram (code ram) 000400h 0003ffh internal register ram upper register file (address with indirect or indexed modes or through windows) (2) 000100h 0000ffh internal register ram lower register file (address with direct, indirect, or indexed modes (2) . 000018h 000017h cpu special function registers (sfr's) (2, 4) 000000h notes: 1. refer to 8xc196kx family user's guide for sfr description. 2. code executed in locations 0000h to 03ffh will be forced external. 3. reserved sfr bit locations must be written with 0. 11
87c196ca/87C196CB ccb (2018h : byte) 0pd e ``1'' enables powerdown 1 bw0 e see table 2wr e ``1'' e wr y /bhee``0'' e wrl y /wrh y 3 ale e ``1'' e alee``0'' e adv y 4 irc0 e see table 5 irc1 e see table 6 loc0 e see table 7 loc1 e see table ccb1 (201ah : byte) 0 ccr2 e ``1'' fetch ccb2 (``0'' for ca) 1 irc2 e see table 2 bw1 e see table 3 wde e ``0'' e always enabled 41 e reserved must be ``1'' 50 e reserved must be ``0'' 6 memsel0 e see table (``1'' for ca) 7 memsel1 e see table (``1'' for ca) ccb2 (201ch : byte) (cb only) 00 e reserved must be ``0'' 1 mode16 e select 16-bit or 24-bit mode 2 remap e ``0''eselect eprom/coderam in segment 0ffh only ( ``1''eselect both segment 0ffh and segment 00h 31 e reserved must be ``1'' 41 e reserved must be ``1'' 51 e reserved must be ``1'' 61 e reserved must be ``1'' 71 e reserved must be ``1'' loc1 loc0 function 0 0 read and write protected 0 1 write protected only 1 0 read protected only 1 1 no protection msel1 msel0 ``cb'' bus timing mode 0 0 mode 0 (1-wait kr) 0 1 reserved must not be used 1 0 reserved must not be used 1 1 mode 3 (kr) mode 0 designed to be similar to the 87c196kr bus (1-wait kr): timing with 1 automatic wait state. see ac timings section for actual timings data. mode 3 (kr): designed to be similar to the 87c196kr bus timing. see ac timings section for actual timings data. irc2 irc1 irc0 max wait states 0 0 0 zero wait states 1 0 0 1 wait state 1 0 1 2 wait states 1 1 0 3 wait states 1 1 1 infinite bw1 bw0 bus width 0 0 illegal 0 1 16-bit only 1 0 8-bit only 1 1 bw pin controlled 12
87c196ca/87C196CB absolute maximum ratings * storage temperature b 60 cto a 150 c voltage from v pp or ea to v ss or angnd b 0.5v to a 13.0v voltage from any other pin to v ss or angnd b 0.5 to a 7.0v this includes v pp on rom and cpu devices . power dissipation1.0w notice: this data sheet contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest data sheet be- fore finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol parameter min max units t a ambient temperature under bias b 40 a 125 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v f osc oscillator frequency 4 20 mhz (4) note: angnd and v ss should be nominally at the same potential. dc characteristics (under listed operating conditions) symbol parameter test conditions min typ max units i cc v cc supply current xtal1 e 20 mhz, ( b 40 cto a 125 c ambient) v cc e v pp e v ref e 5.5v ca (while device in reset) 90 ma cb 100 ma i ref a/d reference supply current 5 ma i idle idle mode current xtal1 e 20 mhz, ca v cc e v pp e v ref e 5.5v 40 ma cb 35 ma i pd powerdown mode current v cc e v pp e v ref e 5.5v (6, 9) 50 tbd m a v il input low voltage (all pins) for port0 (8) b 0.5v 0.3 v cc v v ih input high voltage for port0 (8) 0.7 v cc v cc a 0.5 v v ol output low voltage i ol e 200 m a (3,5) 0.3 v (outputs configured as i ol e 3.2 ma 0.45 v complementary) i ol e 7.0 ma 1.5 v v oh output high voltage i oh eb 200 m a (3,5) v cc b 0.3 v (outputs configured as i oh eb 3.2 ma v cc b 0.7 v complementary) i oh eb 7.0 ma v cc b 1.5 v 13
87c196ca/87C196CB 87C196CB i cc vs frequency 272405 31 87c196ca i cc vs frequency 272405 32 14
87c196ca/87C196CB dc characteristics (under listed operating conditions) (continued) symbol parameter test conditions min typ max units i li input leakage current (std. inputs) v ss k v in k v cc g 10 m a i li1 input leakage current (port 0) v ss k v in k v ref ca g 1.5 m a cb g 1.0 v oh1 slpint (p5.4) and hlda (p2.6) i oh e 0.8 ma (7) 2.0 v output high voltage in reset v oh2 output high voltage in reset i oh eb 15 m a (1) v cc b 1v v c s pin capacitance (any pin to v ss )f test e 1.0 mhz (6) 10 pf r wpu weak pullup resistance (note 6) 150k x r rst reset pullup resistor for cb 65k 180k x r rst reset pullup resistor ca for ca 6k 65k x notes: 1. all bd (bidirectional) pins except inst and clkout. inst and clkout are excluded due to their not being weakly pulled high in reset. bd pins include port1, port2, port3, port4, port5 and port6 except splint (p5.4) and hlda (p2.6). 2. standard input pins include xtal1, ea , reset, and port 1/2/5/6 when setup as inputs. 3. all bidirectional i/o pins when configured as outputs (push/pull). 4. device is static and should operate below 1 hz, but only tested down to 4 mhz. 5. maximum i ol /i oh currents per pin will be characterized and published at a later date. 6. typicals are based on limited number of samples and are not guaranteed. the values listed are at room temperature and v ref e v cc e 5.0v. 7. violating these specifications in reset may cause the device to enter test modes (p5.4 and p2.6). 8. when p0 is used as analog inputs, refer to a/d specifications for this characteristic. 9. for temperatures k 100 c typical is 10 m a. 8xc196cb additional bus timing modes the 8xc196cb device has 2 bus timing modes for external memory interfacing. mode 3: mode 3 is the standard timing mode. use this mode for systems that emulate the 8xc196kr bus tim- ings. mode 0: mode 0 is the standard timing mode, but 1 (mini- mum) wait state is always inserted in external bus cycles. 15
87c196ca/87C196CB ac characteristics (over specified operating conditions) test conditions: capacitance load on all pins e 100 pf, rise and fall times e 10 ns. the 87c196ca/cb will meet these specifications symbol parameter min max units f xtal frequency on xtal1 4.0 20 mhz (1) t osc xtal1 period (1/f xtal ) 50.0 250 ns t xhch xtal1 high to clkout high or low a 20 110 ns t ofd clock failure to reset pulled low (6) 440 m s t clcl clkout period 2 t osc ns t chcl clkout high period t osc b 10 t osc a 15 ns t cllh clkout low to ale/adv high b 15 a 10 ns t llch ale/adv low to clkout high b 20 a 15 ns t lhlh ale/adv cycle time 4 t osc ns (5) t lhll ale/adv high time t osc b 10 t osc a 10 ns t avll address valid to ale low t osc b 15 ns t llax address hold after ale/adv low t osc b 40 ns t llrl ale/adv low to rd low t osc b 30 ns t rlcl rd low to clkout low ca a 4 a 30 ns cb b 8 a 20 ns t rlrh rd low period t osc b 10 ns (5) t rhlh rd high to ale/adv high t osc t osc a 25 ns (3) t rlaz rd low to address float 5 ns t llwl ale/adv low to wr low t osc b 10 ns t clwl clkout low to wr low b 5 a 25 ns t qvwh data valid before wr high t osc b 23 ns t chwh clkout high to wr high b 10 a 15 ns t wlwh wr low period cb t osc b 30 ns (5) ca t osc b 20 t whqx data hold after wr high t osc b 25 ns t whlh wr high to ale/adv high t osc b 10 t osc a 15 ns (3) t whbx bhe , inst hold after wr high t osc b 10 ns t whax ad8 15 hold after wr high t osc b 30 ns (4) t rhbx bhe , inst hold after rd high t osc b 10 ns t rhax ad8 15 hold after rd high t osc b 30 ns (4) notes: 1. testing performed at 4.0 mhz, however, the device is static by design and will typically operate below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only. 5. if wait states are used, add 2 tosc c n, where n e number of wait states. if mode 0 (1 automatic wait state added) operation is selected, add 2 t osc to specification. 6. t ofd is the time for the oscillator fail detect circuit (ofd) to react to a clock failure. the ofd circuitry is enabled by programming the uprom location 0778h with the value 0004h. programming the cde bit enables oscillator fail detec- tion. 16
87c196ca/87C196CB ac characteristics (over specified operating conditions) test conditions: capacitance load on all pins e 100 pf, rise anf fall times e 10 ns. the system must meet these specifications to work with the 87c196ca/cb. symbol parameter min max units t avyv address valid to ready setup 2 t osc b 75 ns (3) t llyv ale low to ready setup t osc b 70 ns (3) t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns (1) t avgv address valid to buswidth setup 2 t osc b 75 ns (2, 3) t llgv ale low to buswidth setup t osc b 60 ns (2, 3) t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3 t osc b 55 ns (2) t rldv rd active to input data valid ca t osc b 22 ns (2) cb t osc b 30 ns (2) t cldv clkout low to input data valid t osc b 50 ns t rhdz end of rd to input data float t osc ns t rhdx data hold after rd high 0 ns notes: 1. if max is exceeded, additional wait states will occur. 2. if wait states are used, add 2 tosc c n, where n e number of wait states. 3. if mode 0 is selected, one wait state minimum is always added. if additional wait states are required, add 2 tosc to the specification. 17
87c196ca/87C196CB 87c196ca/cb system bus timing 272405 17 * if mode 0 operation is selected, add 2 tosc to this time. 18
87c196ca/87C196CB 87c196ca/cb ready timings (one wait state) 272405 18 * if mode 0 selected (cb only), one wait state is always added. if additional wait states are required, add 2 tosc to these specifications. 87C196CB buswidth timings 272405 19 * if mode 0 selected (cb only), add 2 tosc to these specifications. 19
87c196ca/87C196CB 8xc196cb hold/holda timings (over specified operation conditions) test conditions: capacitance load on all pins e 100 pf, rise and fall times e 10 ns. symbol parameter min max units t hvch hold setup time a 65 ns (1) t clhal clkout low to hlda low b 15 a 15 ns t clbrl clkout low to breq low b 15 a 15 ns t azhal hlda low to address float a 20 ns t bzhal hlda low to bhe , inst, rd ,wr weakly driven a 25 ns t clhah clkout low to hlda high b 15 a 15 ns t clbrh clkout low to breq high b 25 a 25 ns t hahax hlda high to address no longer float b 15 ns t hahbv hlda high to bhe , inst, rd ,wr valid b 10 a 15 ns note: 1. to guarantee recognition at next clock. 8xc196cb hold /holda timings 272405 20 20
87c196ca/87C196CB 8xc196cb ac characteristicseslave port slave port waveforme(slpl e 0) 272405 21 slave port timinge(slpl e 0, 1, 2, 3) symbol parameter min max units t savwl address valid to wr low 50 ns t srhav rd high to address valid 60 ns t srlrh rd low period t osc ns t swlwh wr low period t osc ns t srldv rd low to output data valid 60 ns t sdvwh input data setup to wr high 20 ns t swhqx wr high to data invalid 30 ns t srhdz rd high to data float 15 ns notes: 1. test conditions: f osc e 20 mhz, t osc e 60 ns. rise/fall time e 10 ns. capacitive pin load e 100 pf. 2. these values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. specifications above are advanced information and are subject to change. 21
87c196ca/87C196CB ac characteristicseslave port (continued) slave port waveforme(slpl e 1) 272405 22 slave port timinge(slpl e 1, 2, 3) symbol parameter min max units t selll cs low to ale low 20 ns t srheh rd or wr high to cs high 60 ns t sllrl ale low to rd low t osc ns t srlrh rd low period t osc ns t swlwh wr low period t osc ns t savll address valid to ale low 20 ns t sllax ale low to address invalid 20 ns t srldv rd low to output data valid 60 ns t sdvwh input data setup to wr high 20 ns t swhqx wr high to data invalid 30 ns t srhdz rd high to data float 15 ns notes: 1. test conditions: f osc e 20 mhz, t osc e 60 ns. rise/fall time e 10 ns. capacitive pin load e 100 pf. 2. these values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. specifications above are advanced information and are subject to change. 22
87c196ca/87C196CB t e 1 state time (125 ns @ 16 mhz) normal master/slave operation symbol parameter min max units t chch clock period 4t ns t clch clock low time/clock high time 2t b 10 ns (1) t cldv clock falling to data out valid (master) 0.5t 1.5t a 20 ns t cldv1 clock falling to data out valid (slave) 0.5t 1.5t a 50 ns t dvch data in setup to clock rising edge 10 ns t chdx clock rising edge to data in invalid t a 15 ns * timings are guaranteed by design. handshake operation symbol parameter min max units t chch clock period 4t ns t clch clock low time/clock high time 2t b 10 ns (1) t cldv clock falling to data out valid (master) 0.5t 1.5t a 20 ns t cldv1 clock falling to data out valid (slave) 0.5t 1.5t a 50 ns t dvch data in setup to clock rising edge 10 ns t cldx clock rising edge to data in invalid t a 15 ns * timings are guaranteed by design. note: 1. this specification refers to input clocks during slave operation. during master operation, the device will output a nominal 50% duty cycle clock. 272405 34 note: the top scx signal assumes that the ssio is configured to sample on the leading edge with an active-high clock signal. the scx signal will be different for other configurations, however, setup and hold timings will still be the same in relation to the latching edge of scx. figure 6. synchronous serial port 23
87c196ca/87C196CB external clock drive symbol parameter min max units 1/t xlxl oscillator frequency 4 20 mhz t xlxl oscillator period (t osc ) 50.0 250 ns t xhxx high time 0.35 c t osc 0.65 t osc ns t xlxx low time 0.35 c t osc 0.65 t osc ns t xlxh rise time 10 ns t xhxl fall time 10 ns external clock drive waveforms 272405 23 ac testing input, output waveforms 272405 24 ac testing inputs are driven at 3.5v for a logic ``1'' and 0.45v for a logic ``0''. timing measurements are made at 2.0v for a logic ``1'' and 0.8v for logic ``0''. float waveforms 272405 25 for timing purposes a port pin is no longer floating when a 150 mv change from load voltage occurs and begins to float when a 150 mv change from the loading v oh /v ol level occurs i ol /i oh s 15 ma. explanation of ac symbols each symbol is two pairs of letters prefixed by ``t'' for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. conditions: signals: hehigh aeaddress haehlda lelow bebhe leale/adv vevalid brebreq qedata out xeno longer ceclkout rderd valid dedata wewr /wrh /wri zefloating gebuswidth xextal1 hehold yeready 24
87c196ca/87C196CB eprom specifications ac eprom programming characteristics operating conditions: load capacitance e 150 pf; t c e 25 c g 5 c, v cc ,v ref e 5.0v g 0.5v, v ss , angnd e 0v. v pp e 12.5v g 0.25v; ea e 12.5v g 0.25v; fosc e 5.0 mhz. symbol parameter min max units t avll address setup time 0 t osc t llax address hold time 100 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t lllh pale pulse width 50 t osc t plph prog pulse width (2) ca 50 t osc cb 100 t osc t lhpl pale high to prog low 220 t osc t phll prog high to next pale low 220 t osc t phdx word dump hold time 50 t osc t phpl prog high to next prog low 220 t osc t lhpl pale high to prog low 220 t osc t pldv prog low to word dump valid ca 50 t osc cb 100 t osc t shll reset high to first pale low 1100 t osc t phil prog high to ainc low 0 t osc t ilih ainc pulse width 240 t osc t ilvh pver hold after ainc low 50 t osc t ilpl ainc low to prog low 170 t osc t phvl prog high to pver valid 220 t osc notes: 1. run-time programming is done with fosc e 6.0 mhz to 10.0 mhz, v cc ,v pd ,v ref e 5v g 0.5v, t c e 25 c g 5 c and v pp e 12.5v g 0.25v. for run-time programming over a full operating range, contact factory. 2. programming specifications are not tested, but guaranteed by design. 3. this specification is for the word dump mode. for programming pulses use 300 tosc a 100 m s. dc eprom programming characteristics symbol parameter min max units i pp v pp programming supply current 200 ma note: v pp must be within 1v of v cc while v cc k 4.5v. v pp must not have a low impedance path to ground or v ss while v cc l 4.5v. 25
87c196ca/87C196CB eprom programming waveforms slave programming mode data program mode with single program pulse 272405 26 slave programming mode in word dump or data verify mode with auto increment 272405 27 26
87c196ca/87C196CB slave programming mode timing in data program mode with repeated prog pulse and auto increment 272405 28 ac characteristicseserial port-shift register mode serial port timingeshift register mode 0 test conditions: t a eb 40 cto a 125 c; v cc e 5.0v g 10%; v ss e 0.0v; load capacitance e pf symbol parameter min max units t xlxl serial port clock period 8 t osc ns t xlxh serial port clock falling edge to rising edge 4 t osc b 50 4 t osc a 50 ns t qvxh output data setup to clock rising edge 3 t osc ns t xhqx output data hold after clock rising edge 2 t osc b 50 ns t xhqv next output data valid after clock rising edge 2 t osc a 50 ns t dvxh input data setup to clock rising edge 2 t osc a 200 ns t xhdx (8) input data hold after clock rising edge 0 ns t xhqz (8) last clock rising to output float 5 t osc ns note: 8. parameters not tested. 27
87c196ca/87C196CB waveformeserial porteshift register mode serial port waveformeshift register mode 272405 29 a to d characteristics the sample and conversion time of the a/d convert- er in the 8-bit or 10-bit modes is programmed by loading a byte into the ad e time special function register. this allows optimizing the a/d operation for specific applications. the ad e time register is functional for all possible values, but the accuracy of the a/d converter is only guaranteed for the times specified in the operating conditions table. the value loaded into ad e time bits 5, 6, 7 deter- mines the sample time, samp. the value loaded into ad e time bits 0, 1, 2, 3 and 4 determines the bit conversion time, conv. these bits, as well as the equation for calculating the total conversion time, t, are shown in the following table: ad e time 1fafh:byte 76543210 sample time bit conversion time (samp) (conv) 4n a 1 state times n a 1 state times n e 1to7 n e 2to31 equation: t e (samp) a bx (conv) a 2.5 t e total conversion time (states) b e number of bits conversion (8 or 10) n e programmed register value the converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of v ref . v ref must be close to v cc since it supplies both the resistor ladder and the analog portion of the convert- er and input port pins. there is also an ad e test sfr that allows for conversion on angnd and v ref as well as adjusting the zero offset. the abso- lute error listed is without doing any adjustments. a/d converter specification the specifications given assume adherence to the operating conditions section of this data sheet. test- ing is performed with v ref e 5.12v and 20 mhz operating frequency. after a conversion is started, the device is placed in idle mode until the conver- sion is complete. 28
87c196ca/87C196CB 10-bit mode a/d operating conditions symbol description min max units t a ambient temperature b 40 a 125 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v (1) t sam sample time 2.0 m s (2) t conv conversion time 15 18 m s (2) f osc oscillator frequency 4.0 20.0 mhz notes: 1. v ref must be within 0.5v of v cc . 2. the value of ad e time is selected to meet these specifications. 10-bit mode a/d characteristics (using above operating conditions) (6) parameter typ * (1) min max units * resolution 1024 1024 level 10 10 bits absolute error 0 g 3.0 lsbs full scale error 0.25 g 0.5 lsbs zero offset error 0.25 g 0.5 lsbs non-linearity 1.0 g 2.0 g 3.0 lsbs differential non-linearity b 0.75 a 0.75 lsbs channel-to-channel matching g 0.1 0 g 1.0 lsbs repeatability g 0.25 0 lsbs (1) temperature coefficients: offset 0.009 lsb/c (1) full scale 0.009 lsb/c (1) differential non-linearity 0.009 lsb/c (1) off isolation b 60 db (1,2,3) feedthrough b 60 db (1,2) v cc power supply rejection b 60 db (1,2) input resistance 750 1.2k x (4) dc input leakage g 1.0 0 g 3.0 m a voltage on analog input pin angnd b 0.5 v ref a 0.5 v (5) sampling capacitor 3.0 pf * an ``lsb'' as used here has a value of approximately 5 mv. notes: 1. these values are expected for most parts at 25 c, but are not tested or guaranteed. 2. dc to 100 khz. 3. multiplexer break-before-make is guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor. 5. applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 6. all conversions performed with processor in idle mode. 29
87c196ca/87C196CB 8-bit mode a/d operating conditions symbol description min max units t a ambient temperature b 40 a 125 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v (1) t sam sample time 2.0 m s (2) t conv conversion time 12 15 m s (2) f osc oscillator frequency 4.0 20.0 mhz notes: 1. v ref must be within 0.5v of v cc . 2. the value of ad e time is selected to meet these specifications. 8-bit mode a/d characteristics (using above operating conditions) (6) parameter typ * (1) min max units * resolution 256 256 level 8 8 bits absolute error 0 g 1.0 lsbs full scale error g 0.5 lsbs zero offset error g 0.5 lsbs non-linearity 0 g 1.0 lsbs differential non-linearity b 0.5 a 0.5 lsbs channel-to-channel matching 0 g 1.0 lsbs repeatability g 0.25 0 lsbs (1) temperature coefficients: offset 0.003 lsb/c (1) full scale 0.003 lsb/c (1) differential non-linearity 0.003 lsb/c (1) off isolation b 60 db (1,2,3) feedthrough b 60 db (1,2) v cc power supply rejection b 60 db (1,2) input resistance 750 1.2k x (4) dc input leakage g 1.0 0 g 1.5 m a voltage on analog input pin angnd b 0.5 v ref a 0.5 v (5) sampling capacitor 3.0 pf * an ``lsb'' as used here has a value of approximately 20 mv. notes: 1. these values are expected for most parts at 25 c, but are not tested or guaranteed. 2. dc to 100 khz. 3. multiplexer break-before-make is guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor. 5. applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 6. all conversions performed with processor in idle mode. 30
87c196ca/87C196CB 87c196ca design considerations the 87c196ca device is a memory scalar of the 87c196kr device with integrated can 2.0. the ca is designed for strict functional and electrical com- patibility to the kx family as well as integration of on- chip networking capability. the 87c196ca has few- er peripheral functions than the 196kr, due in part to the integration of the can peripheral. following are the functionality differences between the 196kr and 196ca devices. 196kr features unsupported on the 196ca: analog channels 0 and 1 inst pin functionality slpint and slpcs pin support hld/hlda functionality external clocking/direction of timer 1 quadrature clocking timer 1 dynamic buswidth epa capture channels 4 7 (1) external memory. removal of the buswidth pin means the bus cannot dynamically switch from 8- to 16-bit bus mode or vice versa. the pro- grammer must define the bus mode by setting the associated bits in the ccb. (2) auto-programming mode. the 87c196ca de- vice will only support the 16-bit zero wait state bus during auto-programming. (3) epa4 through epa7. since the ca device is based on the kr design, these functions are in the device, however there are no associated pins. a programmer can use these as compare- only channels or for other functions like software timer, start an a/d conversion, or reset timers. (4) slave port support. the slave port can not be used on the 196ca due to a function change for p5.4/slpint and p5.1/slpcs not being bond- ed-out. (5) port functions. some port pins have been re- moved. p5.1, p6.2, p6.3, p1.4 through p1.7, p2.3, p2.5, p0.0 and p0.1. the pxreg, pxssel, and pxio registers can still be updated and read. the programmer should not use the correspond- ing bits associated with the removed port pins to conditionally branch in software. treat these bits as reserved. additionally, these port pins should be setup in- ternally by software as follows: 1. written to pxreg as ``1'' or ``0''. 2. configured as push/pull, pxio as ``0''. 3. configured as lsio. this configuration will effectively strap the pin either high or low. do not configure as open drain output `'1'', or as an input pin. this device is cmos. (6) epa timer reset/write conflict. if the user writes to the epa timer at the same time that the timer is reset, it is indeterminate which will take precedence. users should not write to a timer if using epa signals to reset it. (7) valid time matches. the timer must incre- ment/decrement to the compare value for a match to occur. a match does not occur if the timer is loaded with a value equal to an epa compare value. matches also do not occur if a timer is reset and 0 is the epa compare value. (8) write cycle during reset. if reset occurs dur- ing a write cycle, the contents of the external memory device may be corrupted. (9) indirect shift instruction. the upper 3 bits of the byte register holding the shift count are not masked completely. if the shift count register has the value 32 c n, where n e 1, 3, 5, or 7, the operand will be shifted 32 times. this should have resulted in no shift taking place. (10) p2.7 (clkout). p2.7 (clkout) does not op- erate in open drain mode. 31
87c196ca/87C196CB 87c196ca errata this data sheet was published prior to first available silicon. consequently, there is no known errata at this time. 87c196ca design considerations 1. port0 on the 87c196ca the analog inputs for p0.0 and p0.1 have been multiplexed and tied to v ref . there- fore, initiating an analog conversion on ach0 or ach1 will result in a value equal to full scale (3ffh). on the ca, the digital inputs for these two channels are tied to ground, therefore, reading p0.0 or p0.1 will result in a digital ``0''. 2. port1 on the 87c196ca, p1.4, p1.5, p1.6 and p1.7 have been removed from the device and is unavailable to the programmer. corresponding bits in the port reg- isters have been ``hard-wired'' to provide the follow- ing results when read: register bits when read p1 e pin.x (x e 4,5,6,7) 1 p1 e reg.x (x e 4,5,6,7) 1 p1 e dir.x (x e 4,5,6,7) 1 p1 e mode.x (x e 4,5,6,7) 0 writing to these bits will have no effect. 3. port2 on the 87c196ca, p2.3 and p2.5 have been re- moved from the device and are not available to the programmer. corresponding bits in the port registers have been ``hard-wired'' to provide the following re- sults when read. register bits when read p2 e pin.x (x e 3,5) 1 p2 e reg.x (x e 3,5) 1 p2 e dir.x (x e 3,5) 1 p2 e mode.x (x e 3,5) 0 writing to these bits will have no effect. 4. port5 on the 87c196ca, p5.1 and p5.7 have been re- moved from the device and are not available to the programmer. corresponding bits in the port registers have been ``hard-wired'' to provide the following re- sults when read: register bits when read p5 e pin.x (x e 1,7) 1 p5 e reg.x (x e 1,7) 1 p5 e dir.x (x e 1,7) 1 p5 e mode.x (x e 1) 0 p5 e mode.x (x e 7) 1 writing to these bits will have no effect. 5. port6 on the 87c196ca, p6.2 and p6.3 have been re- moved from the device and are not available to the programmer. corresponding bits in the port registers have been ``hard-wired'' to provide the following re- sults when read: register bits when read p6 e pin.x (x e 2,3) 1 p6 e reg.x (x e 2,3) 1 p6 e dir.x (x e 2,3) 1 p6 e mode.x (x e 2,3) 0 writing to these bits will have no effect. 32
87c196ca/87C196CB data sheet revision history this is the -003 revision of the 87c196ca/cb data sheet. the following differences exist between the -002 version and the -003 revision. 1. the data sheet has been revised to advance from preliminary, indicaitng the specifica- tions have been verified through electrical tests. 2. the 87C196CB 100-ld qfp package and device pinout has been added to the data sheet. 3. the 87C196CB 100-ld qfp device supports up the 16 mbyte of linear address space. 4. the package thermal characteristics for the plcc packages was added to the data sheet, for the cb i ja e 35.0 c/w, i jc e 11.0 c/w. for the ca, i ja e 36.5 c/w and i ja e 10.0 c/w. 5. the an87C196CB pin package diagram was corrected to show ea y as opposed to ea. 6. the remap bit funciton for ccb2 was corrected. setting this bit to 0 selects eprom/ coderam in segment 0ffh only. setting this bit to 1 selects both segment 0ffh and segment 00h. 7. t rlaz has been changed to 5 ns from 20 ns. 8. t wlwh for the ca has been changed to t osc b 20 from t osc b 30. 9. t clgx has been changed to 0 ns min, from t osc b 46 max. 10. timing specifications for the ssio are now add- ed. these timings are currently guaranteed by design. 11. added frequency designation to family nomen- clature figure 2. this is the -002 revision of the 87c196ca data sheet. the following difference exist between the -001 version and the -002 revision. 1. this data sheet now includes the specifications for the 87C196CB as well as the 87c196ca. 2. absolute maximum ratings have been added. 3. maximum frequency has been increased to 20 mhz. 4. maximum icc has been increased from 75 ma to 100 ma for the cb, 90 ma for the ca. 5. idle mode current has been increased to 35 ma from 30 ma for the cb, 40 ma for the ca. 6. input leakage current for port 0 (ili1) was de- creased to 1.5 m a from 2.0 m a for the ca. 7. the electrical characteristics for the can mod- ule were removed. the electrical characteristics for txcan and rxcan are identical to standard port pins. 8. t osc (1/freq) was modified to reflect 20 mhz tim- ings. 9. t ofd (oscillator fail detect specification) for clock failure to reset pin pulled low, was added to the data sheet (4 m s min, 40 m s max) 10. t whqx has been increased to t osc b 25 ns min from t osc b 30 ns min. 11. t rxdx has been replaced by t rhdx .t rlaz has been increased to 20 ns max from 5 ns max. 12. i pp programming supply current has been in- creased to 200 ma from 100 ma. 13. t conv conversion time for 10 bit a/d conver- sions has been decreased to reflect 20 mhz op- eration. 14. r rst was added for the 87c196ca (min e 6 k x /max e 65 k x . 15. t cllh emin/max parameters switched to accu- rately reflect this timing parameter. 16. t rlcl eseparate timings for the 87c196ca vs 87C196CB. t rlcl for the cb is min b 8 ns, max a 20 ns. for the ca, t rlcl min a 4 ns/max a 30 ns. 17. t rlrh changed to t osc b 10 ns from t osc b 5 ns. 18. t avgv added for the 87C196CB. 19. t llgv added for the 87C196CB. 20. t clgx added for the 87C196CB. 21. t rldv eseparate timings for 87C196CB. t rldv max e t osc b 30 ns. for the 87c196ca, t rldv max e t osc b 22 ns. 22. hold/holda timings added for the 87C196CB. 23. slave port timings added for the 87C196CB. 24. separate specifications for t plph for the 87C196CB, t plph , min e 100 t osc . for the 87c196ca, t plph min e 50 t osc . 25. separate specificatons for t pldv for the 87C196CB, t pldv min e 100 t osc for the 87c196ca, t pldv min e 50 t osc . 26. 8-bit mode a/d characteristics added. 33

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